The three-dimensional (3D) integration of two or more semiconductor structures can produce a number of benefits to microelectronic applications. For example, 3D integration of microelectronic components can result in improved electrical performance and power consumption while reducing the area of the device footprint. See, for example, P. Garrou, et al. “The Handbook of 3D Integration,” Wiley-VCH (2008).
The 3D integration of semiconductor structures may take place by the attachment of a semiconductor die to one or more additional semiconductor dice (i.e., die-to-die (D2D)), a semiconductor die to one or more semiconductor wafers (i.e., die-to-wafer (D2W)), as well as a semiconductor wafer to one or more additional semiconductor wafers (i.e., wafer-to-wafer (W2W)), or a combination thereof.
As semiconductor structures are integrated in a 3D configuration, however, the removal of heat from the integrated structures becomes problematic. The density of heat generating devices may be increased in 3D integration processes, without a proportional increase in heat-dissipating outer surface area. The additional heat generated needs to be removed from the 3D integrated structures to prevent failure of the operational devices therein resulting from excessive temperatures.
It has been proposed to incorporate fluid channels having microscale dimensions or smaller (hereinafter referred to as “fluidic microchannels”) into 3D integrated semiconductor structures to allow fluid to flow through the fluidic microchannels during operation of the devices in the 3D integrated semiconductor structures for removal of heat. See, for example, D. Sekar, “A 3D-IC Technology with Integrated Microchannel Cooling,” IEEE 2008, (Georgia Tech).